Electrical Engineering
Introduction to VLSI Systems
4 credits
Static CMOS combinational logic circuits. Standard cells design and layout. Memory element (flip-flop and latch) design. Dynamic logic families. Synchronous logic and timing analysis. Power, scaling, and industry trends. Verification. VHDL/Verilog design, layout and synthesis project using CAD tools. .
Average
76.2%
Students
467
Sections
11
Grade distribution. <50: 15, 50-54: 10, 55-59: 18, 60-63: 20, 64-67: 28, 68-71: 30, 72-75: 40, 76-79: 46, 80-84: 70, 85-89: 67, 90-100: 79.
Historical Averages
2015–2025
Lowest section avg
66.0%
Highest section avg
84.1%
Terms offered
11
Some grade ranges were withheld by UBC to protect student privacy and are not shown above.
Grade data from ubc-pair-grade-data.
| Section | Activity | Status | Time | Instructor |
|---|---|---|---|---|
| 101 | Lecture | Open | Thu 17:00-18:30 | Sudip Shekhar |
| T1A | Discussion | Open | Fri 16:00-18:00 | Sudip Shekhar |
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